Nanotechnology fosters energy-efficient devices that significantly boost on-chip performance for faster, more powerful AI, while also supporting dense integration of sensing and computing, reducing power consumption for advanced on-chip intelligence.
The IEEE International Electron Devices Meeting (IEDM) (https://www.ieee-iedm.org), held annually, brings together researchers and industry professionals to exchange ideas on groundbreaking semiconductor technologies. At this year’s gathering, the spotlight remained firmly on energy-efficient computing, a priority for ensuring that artificial intelligence (AI)’s rapid progress does not lead to inflated energy cost.
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At the same time, the shift toward edge AI — models directly on local devices or at the ‘edge’ of a network — is reshaping archaic computing paradigms. By performing real-time decision-making at the source of data, edge AI relieves the burden on cloud servers. However, placing AI at the edge also comes with design challenges related to power consumption, heat dissipation, and device footprints, spurring innovation in system architecture and hardware.
At Nature Nanotechnology, we closely track and document these developments, showcasing state-of-the-art research at the intersection of nanotechnology and advanced computing, where their synergy drives next-generation on-chip intelligence. For instance, new transistor materials and architectures can be miniaturized to just a few nanometres while maintaining performance. More radically, neuromorphic hardware — an emerging paradigm that mimics the brain’s architecture for highly parallel and efficient processing — leverages nanoscale elements modelled on biological neurons and synapses to deliver real-time, low-latency AI capabilities at the hardware level.
One prominent strategy for achieving on-chip learning and inference is in-memory computing (IMC). By carrying out data processing directly within memory arrays rather than in separate processing units, IMC can dramatically reduce data-transfer overhead. Achieving optimal IMC performance requires the co-design of memory arrays and peripheral circuits, where the trade-offs shaped by various underlying memory technologies make robust metrology essential. Naresh Shanbhag’s group, from the University of Illinois Urbana-Champaign, respond to this need by compiling a benchmarking repository of IMC metrics, to quantify the performance, efficiency, and accuracy; and to analyse the reported IMC data1. They also introduced a methodology on the energy–accuracy–security trade-offs in embedded non-volatile memory-based IMC2. Such trade-offs have been widely acknowledged by researchers during a recent Nature Conference in Beijing (https://conferences.nature.com/event/NeuromorphicComputing), where a variety of IMC paradigms were presented, and emerging asynchronous IMC (event-driven, spike-based, and so on) algorithms and devices have also emerged.
In this issue we bring several approaches that leverage new materials and device functionalities to harness non-volatile memory for IMC. In their Article, Seung Ju Kim et al. introduce halide perovskite materials, a mixed electronic–ionic conductor previously well-known for solar cells and LEDs, to develop neuromorphic devices with uniform ion distribution. They build a 7 × 7 crossbar array based on analogue perovskite synapses, achieving ultra-linear and symmetric synaptic weight control that enhances computation accuracy and efficiency. In another Article, integrating sensing into in-memory computing, Heyi Huang et al. present a fully integrated 1-kb array (pictured on the cover of this issue) with 128 × 8 one-transistor one-optoelectronic memristor cells and silicon CMOS circuits, which features configurable multi-mode functionality in artificial vision systems.
In their Article, Eva Díaz et al. systematically compare the magnetization-switching efficiency of current pulses across seven orders of magnitude in time. By studying spin–orbit torque (SOT) switching in nanoscale devices at various pulse lengths, they reveal that the energy cost for SOT switching decreases by more than an order of magnitude when the pulse duration enters the picosecond range. Their study on how ultrafast switching can substantially reduce power consumption provides important insights for developing spintronics-based memory with improved energy efficiency.
Effective heat dissipation is another key factor in real-world AI applications, particularly in compact systems. In their Article, Kai Wu et al. detail how nanoscale insights can guide the design of thermal interface materials (TIMs), using a gradient heterointerface to achieve near-ideal thermal conductance predicted by theory. Their study narrows the knowledge gap between theoretical predictions and the actual thermal properties of existing TIMs, helping the exploration of new cooling solutions.
On-chip intelligence demands nanoscale insights and innovations at every layer of device and system design. Deepening our understanding of nanoscale phenomena unlocks major performance gains in energy efficiency, thermal management, and reliability. Optimizing individual devices with nanoscale design ensures precise charge control, while the nanofabrication of ultrahigh-density architectures packs billions of cells into a compact footprint. Exploring new nanomaterials — from front-end transistors and memory technologies to back-end interconnects and packaging — broadens our toolkit for creating more efficient, robust systems.
The articles assembled in this issue reflect a growing body of literature on power efficiency and evolving computing paradigms for on-chip intelligence. We stand at an exciting frontier that will redefine what electronic devices can accomplish, and we’re excited to be part of this journey.
